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Senior DSP Software Developer
We are currently looking for a Senior DSP Software developer.
Mandatory Skills/ Experience
Excellent experience in DSP, Audio, software development skills
Good knowledge of algorithm’s and C++.
Experience in Android is a plus.
Analog Design Engineer
Location: Santa Clara, USA
Positions: Multiple (Open)
We have multiple position in Analog Domain for assignment with large semiconductor manufacturer
Mandatory Skills/ Experience-
4+years of experience in designing mixed signal RF / SERDES circuits.
Experience designing SERDES, Driver, Trans Impedence Amplifiers (TIA), Limiting Amplifier (LA), VCO, PLL, Clock and Data Recovery Circuits.
Tools: Cadence Spectre, APS Virtuoso ADE, Assura, Mentor Calibre, Totem.
Candidate should have a H1B or valid permit for work in USA.
Senior DFT Engineer
Positions: 1 (Open)
We are looking for candidate who would be working on the cutting edge products for wireless communication and VOIP technology.
Mandatory Skills/ Experience -
Experience with Advantest Platform.
Knowledge of DFT for Analog and Mixed Signal Designs.
Several years of experience in Semiconductor Industry.
Strong oral and written communication skills.
Senior RF Design Engineer
Desired Skills/Experience -
Deep know how in RF design.
Modelling RF circuits and running AMS simulations.
Knowledge on wireless standards like bluetooth, WiFi, Zigbee.
Contribute in architectural specs and develoment plan.
Support HW/SW development for evaluation, characterization and testing.
Support DFT strategy/implementation Manage/guide circuit block/layout.
Lead Analog and Mixed Signal Designer
Positions : 1 (Open)
We are looking for candidate who would be responsible in cutting edge technologies and developing IC's for smartphone's, wireless audio, tablets and other consumer applications.
Deep working experience in analog design.
Deep knowledge in modelling analog circuits and running AMS simulations.
Support DFT strategy.
Manage circuit/block layout and Architectural specs.
Development of high level model and verification.
Design of CMOS circuits.
Senior ASIC Verification Engineer
Positions : 4 (Closed)
The role would require somebody who has considerable experience in verification conceptsDesired Skills
At least 7+ years of experience, ideally in the range of 7 – 12 years
Experience working on complex verification environments and knowledge of SOC verification concepts
Experience in industry standard verification methodologies (OVM or UVM )
Expertise in System Verilog or equivalent object oriented verification methodology
Experience in writing and executing on complex testplans of both functional blocks and full chip
Experience in full chip validation techniques and Gate Level Simulations
Experience on standard protocols such as SATA/USB/Ethernet etc.
Verification Specman Engineer
Positions : 3 (Closed)
The role would require working on very large and complex ASIC's with high data rates
Job Experience Required -
Long Experience of ASIC Verification with Specman (e language, tools and methodology and building eVC's)
Experience of developing eVC's and test benches, from scratch
Long Experience from block level verification, functional verification, test coverage strategies
Experience of constrained random verification, functional coverage and building verification testbenches with Specman
Experience of working with complex digital ASIC verification with e.g. several DSP's, CPU's and high speed links
Experience from formal verification, e.g. using assertions and constraints Fluent in English
Candidate should be Willing to relocate to this location and work 5 days / week.
Candidates required for help in deployment of DFT methodologies that would reduce test cost and increase production quality.
Strong fundamental knowledge of DFT
Experience in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models.
Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing.
Experience with any standard industry ATPG tools like Synopsys Tetramax, Cadence Encounter Test or Mentor Fastscan
Experience in, VHDL, Verilog RTL, verification, and static timing analysis.
Working knowledge in one or more of the following; C, C++, TCL or Perl.
Experience with industry simulation tools such as VCS, Modelsim, or others.
Experience in silicon bring-up, debug, and validation of DFT features on ATE.
Senior IP Verification Engineer
We are looking for candidate who would be responsible for Verification of moderate to complex IP’s
Desired Skills/Experience -
5 - 8 years of experience in IP Verification
Must have verified atleast 4 - 6 IP’s
Coding in System Verilog, Verilog and VHDL
Programming C, tcl and perl
Good know how in code coverage, functional coverage and assertions
Experience in test bench and test plan development
Team player and good communication skills