REDUCING DESIGN & VERIFICATION TIME

ASIC SoC FPGA Solutions

EDA TOOLS

IC DESIGN & VERIFICATION SERVICES

We provide solutions in complex front end ASIC, SoC and FPGA’s. Verification landscape has changed beyond recognition over the last few years and Verification methodologies and technologies continue to evolve and new flows are still being invented. In spite of all the advances, Verification execution remains one of the biggest challenge and is management's number one pain area.

Realizing Silicon in the face of these challenges requires a workforce capable of adapting and changing on regular basis. Our approach is to develop long-term relationships with our customers, be an extended team to our clients as well as provide challenging and exciting work for our consultans in a friendly, professional working environment.

Verification Planning and Management
Methodology based Verification like UVM, OVM, VMM
Migration from one methodology to other
Verification at various levels like Block, Unit and System level
IP Verification
Functional Verification
Coverage Driven Verification
Gate level Verification
Assertion based Verification
Formal Verification
Development of test benches, Test Plan
Design For Test
ASIC prototyping to FPGA

Physical Design

Physical design has been challenging step in the VLSI/SoC design flow, which converts circuit representation of a design from netlists to complicated geometric representations of shapes for fabrication process of integrated circuits (IC).

The quality of physical design has great impact on chip area, circuit performance, power consumption, reliability, manufacturability, and testability. As process technology advances to 14nm and beyond, the design complexity dramatically increases due to many challenging design considerations, such as thermal effect, signal integrity, sub-wavelength lithography, engineering change order (ECO), inter-die/intra-die variation, analog and mixed-signal layouts, ultra-low-power design.

We deal with following aspects in Physical Design -

Floorplanning, Partitioning, Placement and Routing
CAD for analog, mixed-signal, and RF layouts
Design for ECO, manufacturability, reliability, and testability
Integration with behavior-level and/or logic-level synthesis flows
New physical design methodologies
Timing, power, and signal integrity analysis
Ultra-low-power physical design optimizations

ANALOGUE & MIXED SIGNAL LAYOUT AND DESIGN

ADC, DAC
DC - DC converter
PLL, Oscillator
Amplifiers, Filters
Block and Full Chip Layout
Solutions on lower technology nodes such as 22nm amd 14 nm